// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_vpc_ns_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:27:09 Create file
// ******************************************************************************

#ifndef __STARS_VPC_NS_REG_REG_OFFSET_FIELD_H__
#define __STARS_VPC_NS_REG_REG_OFFSET_FIELD_H__

#define STARS_VPC_NS_REG_SP_LEVEL_LEN    3
#define STARS_VPC_NS_REG_SP_LEVEL_OFFSET 8
#define STARS_VPC_NS_REG_LP_MODE_LEN     3
#define STARS_VPC_NS_REG_LP_MODE_OFFSET  0



#define STARS_VPC_NS_REG_WRR_WEIGHT3_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT3_OFFSET 24
#define STARS_VPC_NS_REG_WRR_WEIGHT2_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT2_OFFSET 16
#define STARS_VPC_NS_REG_WRR_WEIGHT1_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT1_OFFSET 8
#define STARS_VPC_NS_REG_WRR_WEIGHT0_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT0_OFFSET 0

#define STARS_VPC_NS_REG_WRR_WEIGHT7_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT7_OFFSET 24
#define STARS_VPC_NS_REG_WRR_WEIGHT6_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT6_OFFSET 16
#define STARS_VPC_NS_REG_WRR_WEIGHT5_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT5_OFFSET 8
#define STARS_VPC_NS_REG_WRR_WEIGHT4_LEN    8
#define STARS_VPC_NS_REG_WRR_WEIGHT4_OFFSET 0

#define STARS_VPC_NS_REG_SQ_FRIENDLY_VPC_LEN    1
#define STARS_VPC_NS_REG_SQ_FRIENDLY_VPC_OFFSET 14

#define STARS_VPC_NS_REG_DFX_VPC_FSM_SEL_LEN    1
#define STARS_VPC_NS_REG_DFX_VPC_FSM_SEL_OFFSET 0

#define STARS_VPC_NS_REG_DFX_VPC_FSM_OST_CNT_LEN    1
#define STARS_VPC_NS_REG_DFX_VPC_FSM_OST_CNT_OFFSET 8
#define STARS_VPC_NS_REG_DFX_VPC_FSM_STATE_LEN      5
#define STARS_VPC_NS_REG_DFX_VPC_FSM_STATE_OFFSET   0

#define STARS_VPC_NS_REG_VPC_REDUNDANT_RSP_LEN    2
#define STARS_VPC_NS_REG_VPC_REDUNDANT_RSP_OFFSET 0

#define STARS_VPC_NS_REG_VPC_FREE_BITMAP_LEN    2
#define STARS_VPC_NS_REG_VPC_FREE_BITMAP_OFFSET 0

#define STARS_VPC_NS_REG_DFX_VPC_CNT_ENABLE_LEN    1
#define STARS_VPC_NS_REG_DFX_VPC_CNT_ENABLE_OFFSET 0

#define STARS_VPC_NS_REG_DFX_VPC_TASK_VLD_CNT_LEN    32
#define STARS_VPC_NS_REG_DFX_VPC_TASK_VLD_CNT_OFFSET 0

#define STARS_VPC_NS_REG_DFX_VPC_TASK_RSP_CNT_LEN    32
#define STARS_VPC_NS_REG_DFX_VPC_TASK_RSP_CNT_OFFSET 0

#define STARS_VPC_NS_REG_VPC_ENABLE_CTRL_NS_LEN    2
#define STARS_VPC_NS_REG_VPC_ENABLE_CTRL_NS_OFFSET 0

#define STARS_VPC_NS_REG_VPC_DISABLE_CTRL_NS_LEN    2
#define STARS_VPC_NS_REG_VPC_DISABLE_CTRL_NS_OFFSET 0

#define STARS_VPC_NS_REG_VPC_ENABLED_STATUS0_NS_LEN    2
#define STARS_VPC_NS_REG_VPC_ENABLED_STATUS0_NS_OFFSET 0

#define STARS_VPC_NS_REG_VPC_BASE_ADDR_LOW_0_LEN    32
#define STARS_VPC_NS_REG_VPC_BASE_ADDR_LOW_0_OFFSET 0

#define STARS_VPC_NS_REG_VPC_BASE_ADDR_LOW_1_LEN    32
#define STARS_VPC_NS_REG_VPC_BASE_ADDR_LOW_1_OFFSET 0

#define STARS_VPC_NS_REG_VPC_BASE_ADDR_HIGH_0_LEN    17
#define STARS_VPC_NS_REG_VPC_BASE_ADDR_HIGH_0_OFFSET 0

#define STARS_VPC_NS_REG_VPC_BASE_ADDR_HIGH_1_LEN    17
#define STARS_VPC_NS_REG_VPC_BASE_ADDR_HIGH_1_OFFSET 0

#define STARS_VPC_NS_REG_VPC_BASE_ADDR_IS_VIRTUAL_LEN    1
#define STARS_VPC_NS_REG_VPC_BASE_ADDR_IS_VIRTUAL_OFFSET 0

#define STARS_VPC_NS_REG_ADDR_SEC_LOCKER_LEN    32
#define STARS_VPC_NS_REG_ADDR_SEC_LOCKER_OFFSET 0

#define STARS_VPC_NS_REG_VPC_CMDLST_INIT0_0_LEN    32
#define STARS_VPC_NS_REG_VPC_CMDLST_INIT0_0_OFFSET 0

#define STARS_VPC_NS_REG_VPC_CMDLST_INIT0_1_LEN    32
#define STARS_VPC_NS_REG_VPC_CMDLST_INIT0_1_OFFSET 0

#define STARS_VPC_NS_REG_VPC_CMDLST_INIT1_0_LEN    32
#define STARS_VPC_NS_REG_VPC_CMDLST_INIT1_0_OFFSET 0

#define STARS_VPC_NS_REG_VPC_CMDLST_INIT1_1_LEN    32
#define STARS_VPC_NS_REG_VPC_CMDLST_INIT1_1_OFFSET 0

#define STARS_VPC_NS_REG_VPC_CMDLST_KICK_0_LEN    32
#define STARS_VPC_NS_REG_VPC_CMDLST_KICK_0_OFFSET 0

#define STARS_VPC_NS_REG_VPC_CMDLST_KICK_1_LEN    32
#define STARS_VPC_NS_REG_VPC_CMDLST_KICK_1_OFFSET 0

#endif // __STARS_VPC_NS_REG_REG_OFFSET_FIELD_H__
